1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor device having stacked decoupling capacitors.
2. Discussion of Related Art
Semiconductor memory devices such as an SRAM (Static Random Access Memory) have been developed for high speed and high integration applications in electronic systems such as personal computers and communication appliances. To this end, manufacturers of semiconductor memory devices have sought to dispose memory cells within a memory cell region to reduce a critical dimension, increase efficiencies of manufacturing processes, etc. Such an architecture has resulted in layouts having peripheral circuits adjacent to the memory cell region.
For example, decoupling capacitors disposed on a peripheral circuit region within a chip filter noises between operating supplies, e.g., power and ground. Decoupling capacitors disposed on the peripheral circuit region need to provide a large capacitance in a limited area.
An example of a decoupling capacitor is a MOS (Metal Oxide Semiconductor) type capacitor. A gate oxide layer of the MOS transistor is used as a dielectric layer, an impurity diffused region formed on a silicon substrate is used as a first electrode, and a gate layer formed of polysilicon can be used as a second electrode on the gate oxide layer.
A multilayer decoupling capacitor structure in a semiconductor memory device, such as a DRAM (Dynamic Random Access Memory), is shown in FIG. 1.
Referring to FIG. 1 illustrating a sectional structure of multilayer decoupling capacitor, a substrate layer and first, second and third polysilicon layers are used as an electrode of capacitor, to form the multilayer decoupling capacitor. A first polysilicon electrode can be fabricated together with a gate electrode of a cell transistor formed within a memory cell region through a deposition process. Second polysilicon electrodes 62, 64, 72 and 74, and third polysilicon electrodes 60 and 70, are formed within the peripheral circuit region, through a separate process from the fabrication process performed in a memory ell region. The second polysilicon electrodes 62, 64, 72 and 74, and the third polysilicon electrodes 60 and 70, are formed through a separate deposition process in which the memory cell region is masked. For the second polysilicon electrodes 62, 64, 72 and 74, a flow process to contact with n+ regions 76, 78 and 82 is needed. The separate deposition process causes a cost increase.
FIG. 2 illustrates a layout of MOS capacitors that have been fabricated together with MOS transistors. A gate polysilicon region 4 is formed on an active region 2. The active region 2 is a region doped with n+ or p+ type impurity, and forms a first electrode. The gate polysilicon region 4 is a region doped with p+ or n+ type impurity, and forms a second electrode. A dielectric layer of the capacitor becomes a gate oxide layer interposed between a substrate on which the active region 2 and the gate polysilicon region 4 are formed. Where a decoupling capacitor of the MOS type is used to remove power noise, the gate polysilicon region 4 is electrically connected with a metal line 6 through a contact CN1, and the active region 2 is connected with metal lines 9, 10, and 8 through a contact CN2. The metal line 6 is a power line for transferring an operating power source voltage VDD, and the metal line 8 is a ground line for transferring a ground voltage GND to remove power noise and obtain reliable power.
A decoupling capacitor of FIG. 2 is fabricated within the peripheral circuit region through the same process as a transistor of a cell region. The decoupling capacitor is a single capacitor disposed planarly. A decoupling capacitance of the decoupling capacitor of FIG. 2 is less than the decoupling capacitor of FIG. 1, and a decoupling loss can result from a short between the first and second electrodes. The MOS-type decoupling capacitor of FIG. 2 has a low capacitance in a highly-integrated semiconductor device.
A manufacturing process technology for stack type semiconductor memory devices has been developed in conformity with the need for high integration, being changed from a planar layout structure of memory cell transistors of the memory cell region, e.g., in an SRAM. A stack type semiconductor device is fabricated comprising a single stacked memory cell, four N-type MOS transistors as pull-down and pass transistors formed on a semiconductor substrate layer among six MOS transistors constituting a memory cell, and two P-type MOS transistors as load transistors formed on another substrate layer, e.g., channel silicon layer which is insulatively formed on gate electrodes of the N-type MOS transistors.
A semiconductor memory having stacked memory cells achieves high speed and low power, thus the need for removal of various kinds of signal noises and power noises is increased. Therefore, a need exists for a decoupling capacitor having improved capacitance in a limited area.